Integrated circuit devices, commonly known as chips, continue to become more powerful and complex as semiconductor manufacturing technologies have advanced. Whereas early integrated circuit devices included fewer than one hundred transistors, it is now common to integrate several million transistors into a single integrated circuit device. This increased chip density enables some operations that once required several integrated circuit devices to now be implemented in a single integrated circuit device, often providing greater performance at a lower cost. For example, where previously a data processing system might require separate integrated circuit devices for a microprocessor, a memory, a bus interface, and a memory controller, advances in chip density now permit all of these functions to be integrated into the same integrated circuit device. Such devices are typically known as "systems on a chip" due to the high level of integration they provide.
Increases in chip density have also significantly affected the design methodology for integrated circuit chips. When the number of transistors in a particular design was relatively low, it was not particularly difficult for a designer to layout the individual transistors and test the design. As the number of transistors in designs increased, however, the use of cell-based design became more prevalent. With cell-based design, a circuit designer lays out an integrated circuit device design by connecting together a number of predefined "cells". Each cell includes a plurality of transistors that have been integrated together to perform a predefined function. Cells can be maintained in a library, so that a designer can often build a design simply by assembling together cells of transistors, rather than laying out each transistor individually. Moreover, performance and reliability is often improved since each cell can be thoroughly optimized and tested prior to reuse in other designs.
As more complex designs have been developed, the functions incorporated into cells have also become more complex. Particularly complex cells that perform more complex functions are often referred to as "embedded cores", or simply cores. Whereas a cell may represent a relatively simple function such as a logical AND gate or a multiplexer, a core typically represents a more complex function such as that of a processor, a controller, a memory, an interface circuit, or any other complex data processing circuit arrangement. One or more cores may be integrated together in a design, along with any custom-designed support circuitry that is necessary to integrate the cores together.
One advantage of cores is that, like cells, they may be thoroughly tested and simulated by a designer prior to incorporation into an end design. Moreover, cores are typically reusable in other designs so long as predefined interface requirements are met. Due to the significant resources that must to be devoted to designing and testing cores, the ability to reuse a core in other designs can significantly reduce the cost and development time for core-based integrated circuit designs. In fact, a significant market now exists for predefined and pretested cores, whereby many designers now design integrated circuit devices simply by assembling together "soft cores", or the software definition files that define how cores are laid out, developed by and purchased from other designers.
Another net effect of the increase in the complexity of integrated circuit devices is that testing the manufactured devices has become significantly more complex and time consuming. When multiple less-complex integrated circuit devices are utilized in a design, it is often possible to observe and verify the operation of individual devices through external input/output (I/O) pins on the devices. For example, a device may be designed with a boundary scan architecture integrated therein with a chain of registers coupled to the I/O pins of a device. With a boundary scan architecture, the current state of various pins in a device at any given time may be recorded and later accessed via external equipment to verify the operation of a manufactured device.
In addition, built-in self-test (BIST) circuitry may also be incorporated into individual devices to perform predetermined testing operations, e.g., upon power-up of a device. For example, for logic devices such as processors and controllers, logical built-in self-test (LBIST) circuitry may be used to pass pseudo-random test patterns through logic gates to verify their correct operation. For memory arrays, array built-in self-test (ABIST) circuitry may be used to apply test patterns through array elements to verify their operation.
Furthermore, at the chip level and higher, a standard interface, known as the Joint Test Action Group (JTAG) interface (IEEE Std. 1149.1) has been developed to facilitate external access to integrated circuit devices. With a JTAG-compatible integrated circuit device, a standardized test access port (TAP) is provided that permits boundary scan operations to be performed in response to commands issued by an external TAP controller through the TAP port of the device, with the results output back through the same port. Through the standardized interface, card-level and system-level testing is also permitted by interfacing TAP controllers with multiple chips or cards.
Core-based designs, however, introduce new concerns that are not adequately addressed with many testing methodologies. In particular, as designs become more complex, the number of transistors has increased at a greater rate than the number of I/O pins, and thus, it is more difficult to observe the internal operation of such devices. In addition, many cores, e.g., embedded memories, may not be externally accessible at all, and thus may not be tested using external test equipment. Moreover, if BIST is used, different cores may require different BIST circuitry that requires different test methodology and different timing and clock requirements. Furthermore, given that a multi-core design may be based upon cores developed by different entities, there is currently no assurance that any BIST circuitry will be compatible with the other BIST circuitry in a design.
Chip-level and higher interfaces such as the JTAG interface are not readily suited for use with testing multi-core designs since to do so, such interfaces would require individual cores to utilize separate JTAG controllers, thereby requiring controller circuitry to be replicated multiple times on an integrated circuit device, as well as dedicated I/O pins for each controller. Also, such interfaces are not designed to permit multiple, switchable master controllers on the same interface, which may further increase the amount of additional replicated circuitry that would be required to access multiple cores on an integrated circuit device. Considering the expense of additional circuitry and I/O pins that would be required to implement such an interface for this purpose, therefore, significant drawbacks would exist with this approach.
The difficulties in testing core-based designs also raises a broader issue of providing external access to embedded cores for purposes other than testing. Currently, unless specifically tied to a functional interface such as a system bus or direct I/O port, no suitable manner exists for accessing an embedded core. For example, it may be desirable to perform various "service" functions with an integrated circuit device, e.g., integrity testing during manufacturing, reliability testing in operation (e.g., power-on testing), serviceability access (e.g., for configuring a device upon power-up, isolating error conditions or verifying a hardware field repair or upgrade), and early system bring up debug, among others.
Using a functional interface such as a system bus, to perform these service functions typically occupies processing bandwidth and thereby interrupts the normal operation of a device and decreases its performance. Moreover, given the limited number of I/O pins available on most devices, using a direct I/O pin for a service function is often not feasible.
Therefore, a significant need exists for an improved manner of providing external access to embedded cores in a multi-core integrated circuit device, and specifically for the purpose of facilitating testing and other service operations with the embedded cores.